// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:10 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  jtag_reg.v
//
//  General-purpose register that can be read or written via JTAG TAP
//  controller.  Note, this doesn't have seperate shift and update stages,
//  so users of the register must qualify the outputs on update
//
//  Original Author: Chris Jones
//  Current Owner:   Behram Minwalla
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: ameer $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/jtag_reg.v $
//    $DateTime: 2013/12/17 07:13:28 $
//    $Revision: #3 $
//
////////////////////////////////////////////////////////////////////////////// 

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_jtag_reg #(parameter WIDTH=2,
                  parameter [WIDTH-1:0] RST_VAL = 0) (
output reg [WIDTH-1:0]  q,
output wire             serial_out,
input  wire             rst,
input  wire             clk,
input  wire             capture,
input  wire             shift,
input  wire             select,
input  wire [WIDTH-1:0] capture_val,
input  wire             serial_in
);

// Register captures parallel capture_val data when
// clocked but not shifting.  When shifting, LSB is shifted
// onto serial_out and MSB is set via serial_in.
//
assign serial_out = q[0];

// Need to special-case the single-bit case since the shift operation has to look
// different for that case.
// 
generate
  if (WIDTH == 1) begin: single_bit_gen
    always @(posedge clk or posedge rst)
      if (rst)
        q <= RST_VAL;
      else if (select) begin
        if (shift)
          q <= serial_in;
        else if (capture)
          q <= capture_val;
      end
  end 
  else begin: multi_bit_gen
    always @(posedge clk or posedge rst)
      if (rst)
	q <= RST_VAL;
      else if (select) begin
	if (shift)
        q <= {serial_in, q[WIDTH-1:1]};
	else if (capture)
          q <= capture_val;
      end
  end
endgenerate

endmodule
